1. Field of the Invention
The present invention relates to a light emitting display device equipped with a display panel in which light emitting elements constituting pixels are actively driven for example by TFTs (thin film transistors), and to a light emitting display device and a drive control method thereof by which the display quality of an image can be effectively prevented from being deteriorated by a ripple component superimposed for example on a drive source of the display panel.
2. Description of the Related Art
A light emitting display device employing a display panel constituted by arranging light emitting elements in a matrix pattern has been developed widely, and as a light emitting element employed in such a display panel, for example an organic EL (electroluminescent) element in which an organic material is employed in a light emitting layer has attracted attention. This is because of backgrounds one of which is that by employing, in the light emitting layer of the EL element, an organic compound which enables an excellent light emission characteristic to be expected, a high efficiency and a long life which are sustainable for practical use have been advanced.
As a display panel employing such organic EL elements, a simple matrix type display panel in which EL elements are simply arranged in a matrix pattern and an active matrix type display panel in which respective active elements constituted by the above-mentioned TFTs are added to respective EL elements arranged in a matrix pattern have been proposed. The latter active matrix type display panel can realize low power consumption compared to the former simple matrix type display panel and has a characteristic that crosstalk among pixels is small and the like, whereby it is particularly suitable for a high definition display constituting a large screen.
FIG. 1 shows one example of a light emitting display device equipped with a basic circuit structure corresponding to one pixel in a conventional active matrix type display panel, its drive circuit, and a power source circuit supplying a drive power source to a display panel equipped with a large number of the pixels. In the display panel 1, a circuit structure of one pixel 2 is shown for convenience of illustration, and the circuit structure of this pixel 2 shows a most basic pixel structure of a case where an organic EL element is employed as a light emitting element, that is, a case of a so-called conductance controlled method.
That is, a gate electrode (hereinafter simply referred to as a gate) of an N-channel type scan selection transistor Tr1 constituted by a TFT is connected to a scan line (scan line A1), and a source electrode (hereinafter simply referred to as a source) is connected to a data line (data line B1). A drain electrode (hereinafter simply referred to as a drain) of this scan selection transistor Tr1 is connected to a gate of a P-channel type light emission drive transistor Tr2 and to one terminal of a charge-retaining capacitor Cs.
A source of the light emission drive transistor Tr2 is connected to the other terminal of the capacitor Cs and receives supply of a drive power source Va (hereinafter referred to also as a drive voltage Va) from a later-described DC-DC converter via an power source line P1 arranged in the display panel 1. A drain of the light emission drive transistor Tr2 is connected to an anode terminal of an organic EL element E1, and a cathode terminal of this organic EL element E1 is connected to a reference potential point (ground) in the example shown in FIG. 1.
In the circuit structure of the pixel 2, when a selection voltage Select is supplied to the gate of the scan selection transistor Tr1 via the scan line A1 during an address period (data write period), the scan selection transistor Tr1 becomes in an ON state. Upon receiving a data voltage Vdata which corresponds to write data supplied from the data line B1 to the source of the scan selection transistor Tr1, the scan selection transistor Tr1 allows current corresponding to the data voltage Vdata to flow from the source to the drain. Therefore, during a period in which the selection voltage Select is applied to the gate of the transistor Tr1, the capacitor Cs is charged, and the charge voltage becomes one corresponding to the data voltage Vdata.
Meanwhile, the charge voltage charged in the capacitor Cs is supplied to the light emission drive transistor Tr2 as a gate voltage, and current based on the gate voltage of the light emission drive transistor Tr2 and the drive voltage Va supplied via the power source line P1 that is the source voltage flow from the drain thereof to the EL element E1, and the EL element E1 is driven to be lit by the drain current of the light emission drive transistor Tr2.
Here, an addressing operation corresponding to one scan line is completed, and when the gate potential of the scan selection transistor Tr1 becomes an OFF voltage, this transistor Tr1 becomes a so-called cutoff while the drain side of the transistor Tr1 becomes in an open state. However, the gate voltage of the light emission drive transistor Tr2 is maintained by electrical charges accumulated in the capacitor Cs, the same drive current is maintained until the data voltage Vdata is rewritten during a next address period, and a light emission state of the EL element E1 based on this drive current is also continued.
A large number of the structures of the pixel 2 described above are arranged in a matrix pattern in the display panel 1 shown in FIG. 1 to constitute a dot matrix type display panel, and respective pixels 2 are formed at intersection positions between respective scan lines A1, . . . and respective data lines B1, . . .
A video signal to be displayed on the light emission display panel 2 is supplied to a light emission control circuit 4 shown in FIG. 1. In this light emission control circuit 4, based on horizontal and vertical synchronization signals in the video signal, sampling process and the like is imparted to an inputted video signal so that the signal is converted to corresponding pixel data for each pixel, and an operation of writing the converted pixel data in an unillustrated frame memory one by one is executed. During an address period after a writing process of pixel data of one frame in the frame memory is completed, the serial pixel data read out of the frame memory for each one scan line and a shift clock signal are supplied to a shift register and data latch circuit 5a in a data driver 5 one by one.
In this shift register and data latch circuit 5a, pixel data corresponding to one horizontal scan is fetched to be latched utilizing the shift clock signal, so that a latch output corresponding to one horizontal scan is supplied to a level shifter 5b as parallel data. By this operation, the data voltage Vdata corresponding to the pixel data is individually supplied to the source of the scan selection transistor Tr1 constituting each pixel 2. Such an operation is repeated for each one scan during the address period.
A scan shift clock signal corresponding to the horizontal synchronization signal is supplied from the light emission control circuit 4 to a scan driver 6 during the address period. This scan shift clock signal is supplied to a shift register 6a to generate a register output one by one. The register output is converted to a predetermined operational level by a level shifter 6b to be outputted to the respective scan lines A1, . . . By this operation, the selection voltage Select is supplied to the gate of the scan selection transistor Tr1 constituting each pixel 2 for each scan line one by one.
Therefore, the respective pixels 2 arranged on a scan line on the display panel 1 receive a supply of the selection voltage Select from the scan driver 6 for each one scan of the address period. In synchronization with this, the data voltage Vdata is supplied from the level shifter 5b in the data driver 5 to the respective pixels 2 arranged for each scan line, and the gate voltage corresponding to the data voltage Vdata is respectively written in the capacitor Cs in each pixel corresponding to this scan line. By allowing this operation to be implemented covering all scan lines, an image corresponding to one frame is reproduced on the display panel 1.
Meanwhile, the drive voltage Va by a DC-DC converter designated by reference numeral 8 is supplied to the respective pixels 2 arranged on the display panel 1 via the power source lines P1, . . . In the structure shown in this FIG. 1, the DC-DC converter 8 utilizes PWM (pulse width modulation) control so as to boost the output of a primary side DC voltage source Ba.
This DC-DC converter 8 is constructed so as to allow a MOS type power FET Q1 as a switching element to be controlled to be turned on at a predetermined duty cycle by a PWM wave outputted from a switching regulator circuit 9. That is, electrical energy from the primary side DC voltage source Ba is accumulated in an inductor L1 by the ON operation of the power FET Q1, and electrical energy accumulated in the inductor L1 is accumulated in a smoothing capacitor C1 via a diode D1 accompanied by an OFF operation of the power FET Q1. By allowing the power FET Q1 to repeat on-off operations, a boosted DC output can be obtained as a terminal voltage of a capacitor C1.
The DC output voltage is divided by a thermistor TH1 performing temperature compensation and resistors R11 and R12 to be supplied to an error amplifier 10 in the switching regulator circuit 9. In this error amplifier 10, the above-mentioned divided output is compared to a reference voltage Vref, and its comparison output (error output) is supplied to the PWM circuit 11. In this PWM circuit 11, a chopping wave for PWM is generated based on an oscillation signal provided from an oscillator 12 to generate a PWM wave based on this chopping wave and the comparison output. By this PWM wave, a switching operation of the power FET Q1 is performed, and feedback control is performed to hold the output voltage at a predetermined drive voltage Va. Therefore, the output voltage by the DC-DC converter, that is, the drive voltage Va, can be described by the following equation 1:Va=Vref×[(TH1+R11+R12)/R12]  (equation 1)
A pixel structure and a structure of a drive circuit thereof as shown in FIG. 1 are disclosed in Japanese Patent Application Laid-Open No. 2003-316315 which has been already filed by the present applicant, and a DC-DC converter as shown in FIG. 1 is also disclosed in Japanese Patent Application Laid-Open No. 2002-366101 which has been already filed by the present applicant.
Meanwhile, in the structure of the pixel 2 shown in FIG. 1, the drain current Id by which the organic EL element E1 is driven to emit light is determined by the difference (gate-to-source voltage=Vgs of the transistor Tr2) between the drive voltage Va supplied via the power source line P1 and the gate voltage of the drive transistor Tr2 determined by electrical charges accumulated in the capacitor Cs. FIG. 2 shows an equivalent circuit of the pixel structure, and the already described scan selection transistor Tr1 is replaced and represented by a switch SW1. In FIG. 2, the data voltage Vdata transmitted via the data line B1 is equivalently designated by a gate voltage Vgate by a variable voltage source.
Here, for the drive voltage Va supplied to the source of the transistor Tr2, a boosted voltage by the DC-DC converter is employed as already described, and in this type of DC-DC converter, it cannot be avoided that some degree of ripple noise (ripple component) is superimposed on the voltage Va, since the switching operation is accompanied on the operating principle thereof. In the DC-DC converter, although the level of the ripple component can be decreased more when a large capacity smoothing capacitor C1 is employed, decrease effect for the ripple component cannot be expected so much compared to the ratio at which the capacitance thereof is increased.
Particularly, although the demand for the display panel and the DC-DC converter driving this display panel which are shown in FIG. 1 is increasing due to the spread of cellular phones, personal digital assistants (PDAS), and the like, employing a large capacity smoothing capacitor for this type of equipment not only increases the cost but also increases the occupying volume of the capacitor. Thus, restriction on design that the capacitance of the smoothing capacitor has to be restrained to some degree exists as a reality.
Therefore, in the equivalent circuit shown in FIG. 2, the drive voltage on which the ripple component corresponding to a switching cycle (voltage boost cycle Si) of the DC-DC converter is superimposed is supplied to the source of the light emission drive transistor Tr2 as shown as Va in FIG. 3. Meanwhile, the switch SW1 is turned on at an addressing time (data write time), and the gate voltage Vgate based on the video signal is supplied to the gate of the drive transistor Tr2.
Here, Ls in FIG. 3 denotes one scan (line) period in the display panel, and Fs represents one frame period. Since the switching operation in the DC-DC converter is independently activated having nothing to do with one scan period in the display panel, write voltages whose gate-to-source voltages Vgs are different for each scan line influenced by the ripple component are written in the capacitors Cs of the respective pixels.
That is, as shown in FIG. 3, for example, in the capacitors Cs of the respective pixels corresponding to a first scan line, data based on a gate-to-source voltage shown as Vgs1 is written, and in the capacitors Cs corresponding to a second scan line and a third scan line, data based on gate-to-source voltages shown as Vgs2, Vgs3 are written, respectively.
FIG. 4 shows a Vgs/Id characteristic (gate-to-source voltage vs. drain current characteristic) of a TFT represented by the transistor Tr2, and in the case where the gate-to-source voltage changes in the range of ΔVgs, accompanied by this, the drain current also changes in the range of ΔId. Here, it has been known that the organic EL element exhibits a light emission intensity characteristic approximately proportional to the value of the current flowing in this element.
Accordingly, as a result of the state in which the value of Vgs changes influenced by the ripple component in response to timings of addressing as described above, a result that light emission intensities of respective EL elements in the light emitting display panel 1 differ for each scan line is produced. Thus, in the display panel, a problem that the display quality of an image is considerably deteriorated may occur. That is, for example, a fine striped pattern, phenomenon of flicker, or the like may occur.
In order to avoid such a problem, it can be considered that a regulator circuit for example as shown in FIG. 5 is adopted. That is, the regulator circuit shown in FIG. 5 is interposed between the output terminal of the DC-DC converter and the power source lines P1, . . . in the display panel 1. The regulator circuit shown in this FIG. 5 is composed of an NPN transistor Q2, an error amplifier constituted by an op amp OP1, and a reference voltage source Vref1. The emitter potential of the NPN transistor Q2 is supplied to the noninverting input terminal of the op amp OP1, and the electrical potential of the reference voltage source Vref1 is supplied to the inverting input terminal of the op amp OP1.
With this structure, the ripple component generated in the emitter side of the transistor Q2 is outputted to the error amplifier constituted by the op amp OP1. Since the base potential of the transistor Q2 is changed by the output of the error amplifier, as a result, at the emitter side of the transistor Q2, that is, at a Vout side, an output voltage that the ripple component is almost removed can be obtained. However, in the regulator circuit, a power loss of (Vin−Vout)×Iout=P[W] always occurs. Accordingly, due to a problem that the continuous utilization time of a battery is drastically shortened, it is difficult to adopt such a device in the above-mentioned portable equipment under actual conditions.
Thereupon, the present applicant has already filed Japanese Patent Application No. 2004-34401 with respect to a light emitting display device in which a boost frequency in the DC-DC converter by the PWM method is synchronized with a scan signal (synchronized with a frequency that is n times the line frequency) so that for each scan line the same gate-to-source voltage Vgs is constantly supplied to the light emission drive transistor even when a ripple component by a switching operation is superimposed on an operational power source. Thus, a state in which light emitting intensities differ for each scan line can be prevented, and a problem that the display quality of an image is deteriorated, such as occurrence of a fine striped pattern or of a phenomenon of flicker in the display panel, can be effectively dissolved.
However, with the light emitting display device of the above-described structure, since the switching operation in the DC-DC converter is performed by the PWM method, for example, even in a state in which the number of lit pixels of the display is small so that the display is in a state of light load, the switching operation is always performed periodically in the converter. Thus, there is a problem that a useless power loss by the switching operation occurs so that the power utilization rate of a light load time is reduced.